ASIC Design (RTL-GDSII)
ASIC Design (RTL-GDSII)
Technology scaling is leading to nanometer designs and India is becoming one of the major hubs for design and development of ICs, suitable for various applications. This has lead to an increased demand for design engineers who are well versed with industry relevant skills in ASIC design. This short term course on ASCI Design focus on providing a platform for fresh graduates and undergraduates interested to pursue a career in VLSI industry. Here is an opportunity to learn and develop expertise on ASIC design.
What do you gain from this course?
- Learn important concepts and methods related to design, testing, verification and implementation of digital ASICs
- Obtain practical experience in usage of industry standard tools for design and verification of ASICs
- Develop expertise on ASIC design flow from RTL-GDSII
Modules and it’s duration of the course are as mentioned below:
- ASIC Front End Design: 15 days
- ASIC Physical Design: 15 days
- ASIC Verification: 15 days
- Mini Project: 20 days
The Syllabus covered in detail:
Theory and Lab Sessions
Introduction: Introduction to semi-custom ASIC flow, overview of EDA tools for semi-custom IC design flow.
Data Preparation process: Introduction to data preparation functions performing essential tasks for cell libraries which includes creating cell libraries, importing cell data, translating and loading CLF timing data, specifying technology information, power and ground port types, optimizing the standard cell layout, extracting pin and blockage information, setting place and route boundaries and define wire tracks.
Chip input and output pads: Introduction to IO cells, types of IO cells, types of bond pad structures in the IO cell, simultaneous switching noise (SSN), Simultaneous switching output (SSO), driving index (DI) and factor (DF), concept and types of IO packaging, Flip chip IO cell and EM enhancement.
Floor planning and implementation: Introduction to floor planning, TDF/IO constraint files, defining best aspect ratio, core utilization, chip utilization, flat and hierarchical design flow, creating a physical layout.
Power Planning and Management: Need for power management, core and IO level power estimation, limitation of core level and IO level power, placement of power mesh (rectangular rings, straps, trunks) and power pads based on IR and EM based criteria.
Clock Tree Synthesis (CTS): Introduction to CTS, physics of CTS, algorithms for CTS, constraints and device sizing under process variation in CTS, clock distribution network, low skew and power based global, local and useful skew analysis and optimization methodologies.
Routing and Optimization techniques: Taxonomy of routing, routing algorithms, channel and switch box routing, routing operations and optimization, density driven routing, post route optimization for timing, performing design finishing processes, optimizing yield, interactively cleaning up routing DRC, LVS check and errors, antenna checking and fixing violations, crosstalk prevention, analysis and fixing.
Design Signoff: Introduction to design signoff, data preparation flow for power sign off, preparing data for hard/soft macro extracting PG parasitics, performing power and rail analysis based on IR and EM criteria, performing design rule checking and connectivity verification, generating output for back annotation, performing various ECO analysis, industry standard GDSII is generated.
Practical sessions or Hands on sessions: During this sessions, HDL models that have been synthesized and consisting of memory circuits, macros, data path operators, multiple clocks and I/Os will be provided to the participants to carry out physical design and verification process.